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sharc ? mel-100 audio processor adsst-sharc-mel-100 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . summary high pe r f or m a n c e 32-bit au dio pro c es s o r sup e r h a r v ard arch itec ture c o mp uter ( s h a rc ) 4 indep e nde n t b u se s f o r dua l da ta , instruc t ion, a n d nonin t rusiv e , z e r o - o v e rhe a d i/o f e t c h on a singl e c y cle c o de c o mpa t ible with all ot her sharc f a mily d s p s sin g le - i n s truc tion -mu lti p l e - d a t a ( s imd ) c o mput a t ion a l ar chitec ture t w o 32-bit i e ee flo a tin g -point c o m p ut a - tion units , each with a mu ltiplier , al u , shif t e r , and regis t er f i l e se ri al p o r t s o f f e r i 2 s s u p p o r t via 8 prog r a m m ab l e an d s i mult an e o us rec e iv e or tran s m it pin s , wh i c h s u p p or t u p to 16 tr an s m it or 16 rec e iv e c h an n e ls of au dio integ r ated p e r i ph e r a l s in te gr ate d i/ o pro c es s o r , 0.5 mb it on- c h i p sr am, sdr a m c o n t r o ller , glueless mul t ip r o c e ssing f e a t ure s , and i/o p o r t s (se r ia l , l i nk , ex t e r n a l b u s , s p i ? , a n d j t a g ) shar c mel-10 0 suppor t s 32- b i t f i x e d- p o in t , 32-b i t floa t i ng- p oint, and 40-bit flo a ting- p o i nt f o rma t s alu mult data register file (pey) 16 40-bit barrel shifter mult alu data register file (pex) 16 40-bit timer instruction cache 32 48-bit dag1 8 4 32 program sequencer dag2 8 4 32 32 pm address bus dm address bus 32 bus connect (px) pm data bus dm data bus 64 64 core processor spi ports (1) serial ports (4) link ports (2) dma controller 5 16 20 4 iop registers (memory mapped) control, status, and data buffers i/o processor two independent dual-ported blocks addr data data data addr addr data addr processor port i/o port block 0 block 1 dual-ported sram host port addr bus mux multiprocessor interface data bus mux 32 24 external port 6 12 8 jtag test & emulation gpio flags sdram controller ioa 18 iod 64 barrel shifter f i gur e 1 . f u nctio n al bl oc k dia g r a m
adsst-sharc-mel-100 rev. 0 | page 2 of 28 table of contents key features ...................................................................................... 3 general description ......................................................................... 4 hardware architecture ................................................................ 4 software architecture .................................................................. 5 sharc mel-100 family core architecture .............................. 6 sharc mel-100 memory and i/o interface features ............ 9 pin function descriptions ............................................................ 12 boot modes ................................................................................. 17 specifications ................................................................................... 18 recommended operating conditions .................................... 18 electrical characteristics ........................................................... 19 absolute maximum ratings ......................................................... 20 timing specifications ................................................................ 20 power dissipation ...................................................................... 21 output drive currents .............................................................. 21 test conditions ........................................................................... 21 environmental conditions ....................................................... 23 pin configuration ........................................................................... 24 pin layout summary ................................................................. 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history revision 0: initial version
adsst-sharc-mel-100 rev. 0 | page 3 of 28 key features 100 mhz (10 ns) core instruction rate single-cycle instruction execution, including simd operations in both computational units 600 mflops peak and 400 mflops sustained performance 225-ball 17 mm 17 mm mbga package decodes industry-standard formats, using a 32-bit floating- point implementation decoders: dolby? digital, dolby pro logic? ii, dts-es? extended surround (including dts-es discrete and dts-es matrix), dts-96/24, dts neo:6? pcm delay management bass management mpeg-2 aac wavesurround? virtual headphone and virtual loudspeaker downsampling 96 khz to 48 khz (2-channel) single-chip dsp based implementation of digital audio algorithms sharc mel-100 processor features 100 mips i 2 s compatible serial ports interface to external sdram easy interfaces to audio codecs 192 khz processing supports customer specific postprocessing automatic stream detection automatic code loading easy to use software architecture optimized library of routines host communication using spi port supports iec 60958 for bit streams 8-channel output
adsst-sh arc-mel-100 rev. 0 | page 4 of 2 8 gene ral description the s h ar c m e l-100 fa mil y o f p o w e r f u l 32-b i t a u dio p r o c es s o rs f r o m analog d e vices ena b les f l exi b le desig n s an d deli vers a h o st of fe a t ur es acr o ss hig h - e nd and h i g h f i del i ty a u dio sys t e m s to th e a v r e cei v er a nd d v d mark ets. i t in cl ude s m u l t icha n n el a u dio de co ders, en co ders, a nd p o st p r o c ess o rs for dig i t a l a u dio de sig n s usin g dsp s in h o m e t h e a ter sy stem s and au t o m o t i v e au d i o r e c e i v e r s . w i t h 32-b i t a u dio q u ali t y , th e s h ar c m e l-100 a u dio p r o c es s o r a u to dete c t s an d de co des a u dio fo r m a t s in r e a l t i m e , enab lin g end us ers t o en j o y a t h e a t e r - qua l i t y a u dio exp e r i en c e in t h e i r ho me s a n d a u to mo b i l e s . the desig n s can b e c u s t omi z e d t o m e e t t h e exac t r e q u ir emen t s o f th e a p p l ic a t ion. this a u dio d s p sys t e m ena b l e s desig n ers t o mak e val u e addi t i o n s t o p r o d uc t fe a t ur es w o rki n g o f f t h e hig h - e n d b a se fu n c ti o n a l i t y w i th wh i c h t h e y a r e p r o v i d ed . e v a l u a t i o n b o a r d s , s a m p l e a p p l i c a t i o n s , a n d a l l n e c e s s a r y s o f t wa r e s u p p o r t (e .g., dr i v ers) ar e a v a i la b l e . the e v al u a t i on b o a r d enab les oems to o f fer co m p r e h e n s i v e and sin g le-chi p im ple m e n t a t i o n s o f ad van c e d fe a t ur es fo r end-u s er p r o d uc ts. s h ar c m e l-10 0 a u dio p r o c es s o rs ena b le o e ms t o p r o d uce hig h qua l i t y , lo w co st desig n s fe a t ur in g de co d e r a l go r i t h m s a nd p o stpro c e s s o r s for dt s - e s e x te nd e d su r r ou nd ( i nclu d i ng b o t h d t s dis c r e t e 6. 1 a nd d t s m a t r ix 6.1), d t s n e o:6, dol b y dig i tal , dol b y pr o l o g i c ii, aa c, a nd w a v e s u r r o u n d . the cos t o f de ve lo p m en t is r e d u ce d , ena b li n g c o mm on s o l u t i o n s acr o ss p r o d uc t li n e s. f i eld and r e m o tely u p g r ade a b l e p r o d uc ts wi t h pr o g ra mma b l e d s p s and a n op t i mi ze d l i b r a r y o f r o u t i n e s , a l o n g w i th th e b e s t d e v e l o p m e n t t o o l s i n th e i n d u s t r y , re d u c e t h e t i me to m a r k e t . s h ar c m e l-10 0 is t h e com p r e h e n s iv e a n sw er t o t h e n e e d s o f th e hi gh- e n d , h i gh q u ali t y di gi tal a u d i o m a rk et . i t d e l i v e r s a r e a l ist i c hig h f i deli ty a u dio ex p e r i en ce a l o n g w i t h t h e max i m u m n u m b er o f fe a t u r es in t h e p r o d u c t, acr o ss p r ice p o in ts in t h e high-en d h o m e th e a t e r an d d v d ma rk ets. hard w a re ar chitec ture h a r d w a r e a r c h i t ect u r e in c l ud es th e in t e rfa c e bet w een t h e d s p a nd t h e h o st mi cr o c o n t r ol ler , co mman d p r o c essin g , da t a t r a n sfer in s e r i a l a nd p a r a l l el fo r m , da t a b u f f er ma na ge m e n t , a l gor i t h m c o mbi n a t i o ns , m i p s , an d me mor y re qu i r e m e n t s t h a t are prov i d e d . the m u l t icha n n e l a l go r i t h m s a r e im ple m e n t e d o n a sh arc m e l-100 a v r e v al ua tio n bo a r d. th e bo a r d is st a ndalon e and accep t s a co m p r e s s ed dig i tal b i t s t r e a m as s e r i al in p u t f r o m ld/ d vd /c d pla y ers o r st r e a m gen e r a to rs, de c o des t h e b i t st re am , a n d ge n e r a te s a p c m st re am i n re a l t i m e i n 2-cha n n e l o r m u l t icha n n el m o de. i t has a micr o c o n t r ol ler t o ha nd le co mm an ds and o p t i on s e le c t io n s f r o m a sma l l k e y p ad a nd an lcd displa y fo r st a t us d i spla y . sdram 128k 32, boot rom 1m 8 adc dac s/pdif transmitter s/pdif receiver irq gpio serial port multi- channel codec command kernel host micro 03373-0-002 f i g u re 2. s i mp lif ied bl ock d i ag r a m t o u n ders tand t h e s h arc m e l-100 fa mil y ha r d wa r e a r chi t e c t u r e , o n e s h o u l d exa m i n e i t s fo ur ma jor b l o c ks: ? t he c o r e pr o c ess o r ? dual - p o r t e d s r a m ? ex t e rn al p o r t ? inp u t / o u tp u t p r o c e s s o r t h e h a rdw a re a r ch ite c tu re of t h e sh a r c m e l - 1 0 0 i s c o m p l e x . i t has fo ur in de p e n d e n t b u s e s fo r d u a l d a t a , o n e fo r in st r u c t io n s , a nd on e fo r i/o fet c h. sin c e t h e fo ur b u s e s a r e in de p e n d e n t, m u l t i p le t r an s a c t io n s t a k e place wi t h in a sin g le clo c k c y cle. i t has tw o ext e r n a l p o r t s, d m a c h a nne ls, an d eig h t s e r i al p o r t s. i t is a 0.35 n s t e chn o log y i c o p era t in g a t 3.3 v .
adsst-sh arc-mel-100 rev. 0 | page 5 of 2 8 the s h ar c m e l-100 p r o c ess o r ca n be in t e r f ac ed t o ext e r n al p e r i ph erals wi t h r e l a t i v e e a s e . the co mm uni c a t io n b e tw e e n t h e s h ar c m e l-10 0 p r o c es s o r an d a h o s t micr o c on tr ol ler u t ilizes th e s p i b u s. th e h o s t micr o c on t r ol ler ca n be t h e mas t er and t h e s h ar c m e l-10 0 p r o c es s o r can ac t as a sl a v e . th e p e r i p h erals ca n be co n t r o lled b y th e h o s t m i cr oco n tr o l le r us i n g th e s p i b u s. the co m m uni c a t io n is b a s e d on co mmands and p a r a m e ters. s t a t us i n fo r m a t i o n r e ga r d ing t h e s h arc m e l-1 00 de co di n g is p e r i o d ica l ly u p d a te d an d made a v a i la b l e to t h e h o st micr o c o n t r ol ler . the b l o c k dia g r a m o f the s h ar c m e l-100 (s e e f i gur e 1) ill u s t ra t e s t h e f o llo w in g a r c h i t ec t u ral f e a t ur es: ? c o mp u t at i o n u n i t s ( a l u , mu l t i p l i e r , a n d s h i f t e r ) w i t h a share d d a t a re g i ste r f i l e ? da t a addr es s g e n e ra t o r s (d a g 1 , d a g2) ? p r ogra m seq u en cer wi t h in s t r u ctio n cache ? t i m e r s wi th ev en t ca p t ur e m o de s ? on - c hi p , d u al-p o r t e d s r a m ? e x te r n a l p o r t fo r i n te r f a c i n g to of f - ch i p me mor y and pe ri p h e r al s ? h o st p o r t an d sdr a m in t e r f ac e ? dm a c o n t ro l l e r ? enhan c e d ser i al p o r t s ? jt a g t e s t ac cess p o r t w e wil l us e f i g u r e 2 as o u r r e f e r e n c e . the s h ar c m e l-100 co mm unic a t es wi t h t h e h o s t micr o c o n tr ol ler u s in g s p i. th e s h ar c m e l-10 0 has a n on-c hi p m e m o r y b u f f er tha t is us ed f o r s t o r in g co mman ds /p a r am et ers s e n t b y t h e h o s t t o t h e sh arc m e l-100 and als o s t a t us inf o r m a t io n f r o m the s h ar c m e l-100. ther e is a def i ne d p r o t o c ol fo r p a ssin g co m m an ds and ob ta inin g s t a t us inf o r m a t io n. o n ce t h e s h ar c m e l-100 r e cei v es a co mma nd f r o m t h e h o s t micr o , i t w i l l p r o c es s t h e co mman d an d i n fo r m t h e h o s t micr o a b o u t t h e s t a t us. th es e co mman d s i n i t i a te ac t i o n s such as enco di n g and de co ding. en co din g an d d e co di n g wi l l r e su l t in d a t a p r o c essin g and t h e p r o c ess e d d a t a ma y b e del i ver e d o v er t h e s e r i a l p o r t . f o r exa m ple , w h i l e en co ding, t h e mp3 da t a is acc e p t e d t h r o ug h t h e s e r i al p o r t f r o m p e r i p h erals li k e a n ad c o r s/pd if r e cei v er . the mp3 da t a i s t h e n e n co de d a nd sto r e d i n a n o n -ch i p co m p r e s s e d da t a b u f f er . th e s h ar c m e l - 100 wil l p r ep a r e th e co m p r e s s e d f r am es in iec 958 f o r m a t s o tha t t h ey can b e s e n t o u t usin g the s e r i al p o r t o r s/pd if tra n smi t t e r . u s in g t h e s e r i al p o r t , co m p r e s s e d f r a m es ca n b e do wnlo aded t o th e s h arc m e l-100, w h er e they ca n b e dec o ded , and t h e r e s u l t in g mp3 da ta ca n b e se n t o n th e se ri al po r t tra n sm i t t e r . w h ile co mm a n d s a nd da t a a r e t r an sfer r e d b e twe e n t h e h o st micro c o n t r ol ler a nd th e s h arc m e l - 100 o v er th e s p i, r e lia b le comm unic a t ion n e e d s t h e h e l p of in t e r r u p ts an d a fe w ge n e ra l - pur p os e in p u t/o u t p ut li nes. soft w a re ar chitec ture the a u dio p r o c es s o rs f r o m analog d e vi ces ena b le desig n ers to mak e val u e addi t i o n s t o p r o d uc t fe a t ur es w o rki n g o f f t h e hig h - end bas e f u n c t i o n ali t y . the s h ar c m e l - 100 s o f t wa r e has the fol l o w ing p a r t s: ? e x e c u t i v e k e r n el ? alg o ri th m a s li b r a r y m o d u le the exe c u t i v e k e r n e l has t h e fol l o w in g f u n c t i o n s: ? p o we r - up h a rd w a re i n it i a l i z a t i on ? se ri a l p o rt m a n a g e m e n t ? au t o m a t i c s t r e a m d e t e c t ? a u t o ma tic co de lo ad ? c o m m a nd pro c e s s i ng ? i n te r r upt h a nd l i ng ? da t a b u f f e r m a n a g e m e n t ? c a l l in g lib r a r y m o d u le ? st a t u s re p o r t the exe c u t i v e k e r n e l g e ts exe c ut e d as s o o n as b o o t in g t a k e s p l a c e. t h e h a rd w a re re s o u r c e s are i n it i a l i z e d i n t h e b e g i n n i n g . the co mman d b u f f er a n d g e ne ral-p u r p os e p r og ra mma b l e f l ag pi ns are i n i t i a l i z e d. v a r i ou s d a t a b u f f e r s and me mor y v a r i abl e s a r e ini t ial i ze d . i n t e r r u p ts a r e p r og ra mm e d an d ena b le d . th en, def i ni te sig n a t u r es a r e wr i t t e n c o mman d b u f f er t o info r m t h e h o s t tha t t h e s h ar c m e l - 100 is r e ad y t o r e cei v e th e co mman d s. o n ce co mman d s ar e is s u ed b y t h e h o s t m i cr oco n tr o l l e r , th ey a r e e x ecu t ed a n d a p p r o p ria t e a c t i o n s tak e place. d e c o di n g is ha nd le d b y issuin g a p p r o p r i a t e co mmands f r om t h e ho st m i c r o c on t r o l l e r . the k e r n e l co mm unic a t es w i t h t h e l i b r a r y m o d u le fo r a p a r t ic u l a r a l go r i t h m i n a def i n e d wa y . t h e det a i l s a r e fo un d i n th e s p eci f i c im pl e m en t a ti o n d o cum e n t s . a s t h e k e rn e l i s m o d u la r , i t is e a sy t o c u s t o m ize t o dif f er en t ha rd wa r e p l a t f o r m s. m o s t o f t h e t i me , us ers n e e d t o cha n g e t h e ini t i a liza t i o n c o de to s u i t t h e p a r t ic u l a r co dec ch os en. decoding library executive kernel input stream output stream fi g u r e 3 . s o f t w a r e the s h ar c m e l-100 in c l udes a 100 mh z co r e , d u al-p o r t e d on- c h i p s r am, a n in teg r a t ed i/o p r o c es s o r wi th m u l t i p r o ces s ing s u p p o r t, an d m u l t i p le in t e r n al b u s e s t o e l imina t e i/o bot t lene c k s. the s h arc m e l-1 00 o f f e rs a s i n g le-i ns tr uc tio n - m u lt ip l e - d a t a ( s i m d ) a r c h it e c t u re , u s i n g t w o c o m p ut a t i o n a l uni t s. f a b r ic a t e d in a st a t e-o f -t h e -a r t , hig h sp e e d , lo w p o w e r cm os p r o c es s, th e s h arc m e l - 100 has a 10 ns in s t r u c t io n cy c l e t i m e .
adsst-sharc-mel-100 rev. 0 | page 6 of 28 d computational hardware running at 100 mhz, 00 continues the sharcs industry-leading n g architectural features: u, e ur 32-bit re ? (0.5 mbit) ess interface to sdrams mory peripherals 00 ? d interface pins rocessor system. a with its sim the sharc mel-100 can perform 600 million math operations per second. table 1 shows performance benchmarks for the sharc mel-100. the sharc mel-1 standards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include a 1-mbit dual-ported sram memory, a host processor interface, an i/o processor that supports 14 dma channels, four serial ports, two link ports, a sdram controller, an spi interface, an external parallel bus, and glueless multiprocessing. figure 2 illustrates the followin ? two processing elements, each made up of an al multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cach ? pm and dm buses capable of supporting fo data transfers between memory and the core every co processor cycle interval timer ? on-chip sram ? sdram controller for gluel ? external port that supports ? interfacing to off-chip me ? glueless multiprocessing for six sharc mel-1 processors ? host port read/write of iop registers ma controller ? four serial ports ? two link ports ? spi compatible ? jtag test access port ? 12 general-purpose i/o figure 4 shows a typical single-p multiprocessing system appears in figure 8. sharc mel-100 family core architecture the sharc mel-100 includes the following architectural features of the adsp-2116x family core: simd computational engine the sharc mel-100 contains two computational processing elements that operate as a single instruction multiple data (simd) engine. the processing elements are referred to as pex and pey, and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. this architecture is efficient at executing math- intensive dsp algorithms. entering simd mode also has an effect on the way data is transferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, paralle l computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform single-cycle instructions. the three units within each processing element are arranged in parallel, maximizing computational throughput. single multifunction instructions execute parallel alu and multiplier operations. in simd mode, the parallel alu and multiplier operations occur in both processing elements. these computation units support ieee 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats. table 1. benchmarks (at 100 mhz) benchmark algorithm speed (at 100 mhz) 1024 point complex fft (radix 4, with reversal) 1 171 s fir filter (per tap) 1 5 ns iir filter (per biquad) 1 40 ns matrix multiply (pipelined) [3 3] ? [3 1] 30 ns [4 4] ? [4 1] 37 ns divide (y/x) 60 ns inverse square root 40 ns dma transfers 800 mbytes/s 1 assumes two filters in multichannel simd mode
adsst-sh arc-mel-100 rev. 0 | page 7 of 2 8 dma device (optional) data clkout dmar1?2 dmag1? 2 addr data host processor interface (optional) 3 12 clock clkin xtal irq2-0 2 clk_cfg1?0 eboot lboot flag11?0 timexp clkdbl reset jtag 7 sbts adsst sharc mel-100 bms link devices (2 max) (optional) lxclk lxack lxdat7 ? 0 sclk0 d0b d0a fs0 serial device (optional) cs boot eprom (optional) addr memory and peripherals (optional) oe data cs rd ras ack br1?6 rpba id2-0 pa hbg hbr sdwe ms3? 0 wr data47 ? 1 6 data addr cs ack we addr23 ? 0 data control addre s s brst sdram (optional) sclk1 d1b d1a fs1 sclk2 d2b d2a fs2 sclk3 d3b d3a fs3 spiclk miso mosi spids spi compatible device (host or slave) (optional) data cas ras dqm we addr cs a10 cke clk dqm cas redy sdcke sda10 sdclk1?0 rstout serial device (optional) serial device (optional) serial device (optional) 03681- 0- 001 f i g u re 4. sy s t e m b l ock d i ag r a m dat a r e gister file a g e neral-p u r p os e da ta r e g i s t er f i le is co n t a i n e d in e a c h p r o c es sin g e l e m en t. the r e g i s t er f i les t r a n sfer da t a b e twe e n t h e co m p u t a t ion un i t s and t h e da t a b u s e s, a nd sto r e in ter m e d i a te r e s u l t s. th es e 1 0 -p o r t, 32-r e g i s t er (16 p r ima r y , 16 s e co nda r y) r e g i s t er f i les, co m b i n e d wi t h t h e s h arc m e l-1 00 s enhance d h a r v ard arch ite c t u re, e n abl e u n c o nst r ai ne d d a t a f l ow b e t w e e n co m p u t a t ion un i t s and in t e r n a l m e m o r y . t h e r e g i st ers in pe x a r e r e fer r e d t o as r0Cr15, an d i n pe y as s0Cs1 5 . single-c ycl e f e tch of ins t r u c t ion an d fou r ope r a n ds the s h ar c m e l-100 f e a t ur es a n enhan c e d h a r v a r d a r c h i t e c t u r e in whic h t h e da t a m e m o r y (d m) b u s tra n sfers da ta a nd t h e p r og ra m m e m o r y (pm) b u s tra n sfers bo th in s t r u c t io n s a nd da t a (s e e f i gur e 4). w i t h t h e s h arc m e l-1 00 s s e p a r a te p r o g r a m a nd da t a m e m o r y b u s e s a nd o n -ch i p i n st r u c t io n cache, t h e p r o c e s s o r can sim u l t an e o us ly fet c h fo ur o p era n ds (t w o o v er e a ch da t a b u s) a nd a n in st r u c t io n (f r o m t h e cach e), a l l wi t h i n a sin g le c y c l e . instru ction ca che the s h ar c m e l-100 in c l udes a n o n -c hi p in s t r u c t io n cach e tha t ena b les 3- b u s o p era t ion fo r fet c hin g an inst r u c t io n an d fo ur da t a v a l u es. th e cach e is s e le c t iv eo n l y t h e in st r u c t io n s w h os e fet c h e s co nf lic t wi t h pm b u s da ta access es a r e c a c h e d . this ca ch e e n a b l e s full s p eed e x ecu t i o n o f co r e , l o o p ed o p e r a t i o n s s u c h a s d i g i t a l f i lte r m u lt ip l y - a c c u m u l a te s a n d f f t bu tte r f l y pro c e s s i ng . dat a a d dress gener a tors wi th hardw a r e circul ar b u ff e r s the s h ar c m e l-100 p r o c ess o r s tw o da t a addr es s g e n e r a t o rs (d a g s) a r e us e d fo r in dir e c t addr es sin g and im plem e n t i n g c i rc u l ar d a t a bu f f e r s i n h a rdw a re. c i rc u l ar bu f f e r s e n abl e e f f i c i e n t pro g r a m m i ng of d e l a y l i ne s a n d ot he r d a t a st r u c t u r e s r e q u ir e d in dig i tal sig n al p r o c essin g , an d a r e comm onl y us e d in dig i t a l f i l t ers and f o ur ier t r a n sf o r m s . th e tw o d a gs o f t h e s h ar c m e l-10 0 co n t a i n s u f f i ci en t r e g i st ers t o ena b le t h e cr ea tio n o f u p to 32 cir c u l a r b u f f ers (16 p r ima r y r e g i s t er s e ts, 16 s e co nd a r y ) . the d a gs a u toma t i c a l l y ha nd le addr ess p o in te r
adsst-sh arc-mel-100 rev. 0 | page 8 of 2 8 w r a p arou n d , re d u c e ove r he a d , i n c r e a s e p e r f or m a n c e, a n d sim p lif y im ple m e n t a t i o n . c i r c u l a r b u f f ers ca n st a r t an d e nd a t an y me mor y l o c a t i o n . flexible instruction set the 48- b i t in st r u c t io n w o r d acc o mmo d a t e s a v a r i ety o f p a ra l l e l o p era t io n s f o r co n c ise p r ogra mmin g . f o r exa m p l e , th e s h ar c m e l-100 can con d i t io nal l y exec u t e a m u l t i p l y , an add , an d a s u b t ra ct i n bo t h p r oce s s i n g e l em en t s , w h il e b r a n c h i n g , all wi t h in a sin g le i n st r u c t io n. 0x000a 0000 ? 0x000a 7fff (blk 1) 0x0002 8000 ? 0x0002 9fff (blk 1) 0x0005 0000 ? 0x0005 3fff (blk 1) 0x0010 0000 ? 0x0011 ffff 0x0004 0000 ? 0x0004 3fff (blk 0) 0x0008 0000 ? 0x0008 7fff (blk 0) 0x0012 0000 ? 0x0013 ffff 0x0014 0000 ? 0x0015 ffff 0x0016 0000 ? 0x0017 ffff 0x001a 0000 ? 0x001b ffff 0x0000 0000 ? 0x0001 ffff 0x0002 0000 ? 0x0002 1fff (blk 0) 0x0020 0000 bank 1 ms0 bank 2 ms1 bank 3 ms2 ms3 iop registers long word addressing short word addressing normal word addressing address bank 0 0x03ff ffff (sdram) 0x00ff ffff (non-sdram) 0x0400 0000 0x07ff ffff (sdram) 0x04ff ffff (non-sdram) 0x0800 0000 0x0bff ffff (sdram) 0x08ff ffff (non-sdram) 0x0c00 0000 0x0fff ffff (sdram) 0x0cff ffff (non-sdram) note: bank sizes are fixed 0x0018 0000 ? 0x0019 ffff address reserved 0x0 01c ffff 0x0 01f ffff external memory space iop registers of adsst-sharc-mel-100 with id = 110 iop registers of adsst-sharc-mel-100 with id = 101 iop registers of adsst-sharc-mel-100 with id = 100 iop registers of adsst-sharc-mel-100 with id = 011 iop registers of adsst-sharc-mel-100 with id = 010 iop registers of adsst-sharc-mel-100 with id = 001 multiprocessor memor y space interna l memor y space f i gure 5 . memo r y ma p b l ock d i a g r a m
adsst-sh arc-mel-100 rev. 0 | page 9 of 2 8 shar c mel - 100 memor y and i/o interf a c e fea t ures the s h ar c m e l-100 adds the f o l l o w in g a r c h i t ec t u ral f e a t ur es t o th e ads p -21 16x fa mil y co r e : on-chip me m o ry the s h ar c m e l-100 con t a i n s 0.5 mb i t o f o n -chi p s r am. off-chip me m o ry and perip h er als int e rf ace the s h ar c m e l-100 s ext e r n al p o r t p r o v ides th e p r o c es s o r s in t e r f ace t o o f f-c h i p m e m o r y a nd p e r i ph erals. the 62.7 m w o r d o f f-c h i p addr es s s p ace (254 m w o r d if al l s d ram) is in c l ude d in th e s h arc m e l - 100 p r o c es s o r s unif ied addr es s s p ace . th e se pa ra t e o n - c h i p b u se s f o r p m a d d r e s se s , pm da ta , d m addr ess e s, d m d a t a , i/ o ad dr ess e s, a nd i/o d a t a a r e m u l t i p lexe d a t t h e ext e r n al p o r t t o cr e a t e an exter n al sys t em b u s wi t h a sin g le 24 -b i t addr es s b u s a nd a sin g le 32 -b i t da ta b u s. e v er y acces s t o ext e r n al m e m o r y is bas e d on an addr es s tha t fetches a 3 2 - bi t wo r d . w h en fetching an inst r u c t io n f r o m e x te r n a l me mor y , t w o 3 2 - bi t d a t a l o c a t i ons are b e i n g a c c e s s e d f o r pa c k ed in s t r u cti o n s . u n u s ed l i nk po r t l i n e s c a n al so be u s ed as add i t i o n a l d a t a li n e s d a t a [0]Cd a t a [15], en a b li n g si n g le- c y cle e x e c u t io n o f in st r u c t io n s f r o m ext e r n a l mem o r y a t u p t o 100 mh z. f i gure 6 s h o w s t h e al ig nmen t o f va r i o u s acces s es t o e x te r n a l me mor y . 47 40 39 32 31 24 23 16 15 8 7 0 extra data lines data[15 ? 0] are only accessible if link ports are disabled. enable these additional data lines by selecting ipack[1:0] = 01 in syscon l1data[7:0] data 15 ? 8 l0data[7:0] data7 ? 0 prom boot 8-bit packed dma data 8-bit packed instruction execution 16-bit packed dma data 16-bit packed instruction execution float or fixed, d31 ?d0, 32-bit packed 32-bit packed instruction data 47 ? 16 data 15 ? 0 48-bit instruction fetch (no packing) f i gure 6. e x te rn al d a t a a l ignm ent o p tions t h e e x te r n a l p o r t supp or t s a s y n ch ronou s , s y nc h r onou s , an d s y nc h r onou s bu r s t a c c e ss . s y nc h r onou s bu r s t sr a m c a n b e in ter f ace d g l uel e ssly . t h e s h a r c m e l-100 can a l s o in ter f ace g l u e l e ssly to s d r a m . a d dre s s i ng of an e x te r n a l me mor y de v i c e is faci li t a te d b y o n -ch i p de co di n g o f hig h -o r d e r addr ess li n e s to g e n e r a t e m e m o r y ba nk s e lec t sig n als. th e s h ar c m e l-100 p r o v ides p r og ra mma b l e m e m o r y wa i t s t a t e s and ext e r n al me mor y a c k n o w l e d g e c o n t ro l s to e n abl e i n te r f a c i n g to me mor y a nd p e r i ph er a l s wi t h va r i ab le ac cess, h o ld , and d i s a b l e t i m e re qu i r e m e n t s . sdram int e rface the s d ram in t e r f ace ena b les t h e s h arc m e l-100 t o tra n sf er d a t a to an d f r om s y nch r o n ou s dr a m ( s dr a m ) a t t h e c o re clo c k f r e q uen c y o r o n e-half t h e co r e clo c k f r e q uen c y . th e s y nc h r onou s a p pro a ch , c o upl e d w i t h t h e c o re cl o c k f r e q u e nc y , s u p p o r t s d a ta tra n sf e r a t a hi gh th r o ugh p u t u p t o 400 mb yt es/s f o r 32-b i t tra n sf ers a nd 600 mb ytes/s f o r 48-b i t t r a n sfers. th e sd r a m in t e r f ac e p r o v ides a g l u e les s in t e r f ace wi t h s t anda r d s d rams (16 mb i t , 64 mb i t , 128 mb i t , an d 256 mb i t ) and in c l udes o p t i o n s t o s u p p o r t addi tio n al b u f f ers betw een t h e s h ar c m e l - 100 and s d ram. the s d ram in t e r f ace is ext r eme l y f l exi b le and p r o v ides c a p a b i li ty fo r co nnec t in g s d rams t o an y o n e o f t h e s h arc m e l-100 p r o c es s o r s f o ur ext e r n al m e m o r y ba nks, wi th u p t o al l f o ur ba nks ma p p e d to s d r a m. s y s t em s wi th s e veral s d r a m d e v i ce s co nn ect e d in pa rall e l ma y r e q u i r e b u f f eri n g t o m eet o v eral l sys t em timin g r e q u ir em en ts. th e s h arc m e l-100 su p p o r ts p i p e l i nin g o f t h e address an d con t r o l sig n a l s to ena b le s u c h bu f f e r i n g b e t w e e n it s e l f a n d m u lt ip l e sd r a m d e v i c e s . targ et bo ar d jtag em ulato r c o nne ctor analog devices ds p t o ols p r o d uc t lin e o f j t a g em u l a t o r s us es th e ieee 1149.1 jt a g t e s t ac cess p o r t o f th e s h ar c m e l - 100 p r o c es s o r t o m o ni t o r and co n t rol t h e t a rg et b o ar d p r o c es s o r d u r i ng e m u l a t i o n . a n a l o g d e v i c e s d s p t o o l s pro d u c t l i ne of j t a g e m u l a t or s prov i d e s e m u l at i o n at f u l l pro c e s s o r sp e e d, ena b lin g in sp e c t i o n and m o dif i ca t i on o f me m o r y , r e g i sters, a n d p r o c es s o r s t acks . th e p r o c es s o r s jt a g in t e r f ace en s u r e s t h a t th e em ula t o r w i ll n o t a f f e ct ta r g e t sys t em loa d i n g o r ti m i n g . f o r co m p let e info r m a t ion o n an a l og d e v i ces d s p t o ols p r o d uc t l i ne of j t a g e m u l a t or op e r at i o n , s e e t h e a ppr opr i a t e em u l at o r h a rdw a re u s e r ' s g u i d e . f o r det a i l e d info r m a t ion o n t h e i n t e rfa c i n g o f a n al og devi ce s jt a g em ula t o r s w i t h a n al og de v i c e s d s p p r od u c t s w i t h jt a g e m ula t i o n po r t s , p l ea se r e f e r t o t h e e n g i n e er -t o-en g i ne er n o t e ee-68, a n a l og d e v i c e s j t a g em u l a t i o n t e chni c a l r e f e re n c e . b o th o f th e s e docum e n t s ca n b e fo un d on t h e a n alog d e v i ces w e bsi t e a t : h t t p :/ /w w w . a na l o g.co m/ dsp/ te ch_do c s. h t m l dma controll er the s h ar c m e l-100 p r o c ess o r s o n -c hi p d m a co n t r o l l er ena b les zer o -o v e rh e a d da ta tran sfers wi t h o u t p r o c es s o r in t e r v en t i o n . th e d m a co n t r o l l er o p era t es in dep e n d e n t l y a nd in visib l y t o t h e p r o c es s o r co r e , ena b lin g d m a o p era t io ns t o o c c u r w h i l e t h e co r e is sim u l t ane o us l y exe c u t in g i t s p r og ra m in st r u c t io n s . d m a t r a n sfers can o c c u r b e tw e e n t h e s h arc m e l-100 p r o c ess o r s in ter n al mem o r y a nd ext e r n al m e m o r y , ext e r n al p e r i pherals, o r a h o s t p r o c es s o r . d m a t r a n sfers ca n als o o c c u r between t h e s h ar c m e l-100 p r o c ess o r s in ter n al m e m o r y a nd i t s s e r i al p o r t s, lin k p o r t s, o r th e s p i (s er ial pe ri p h e r al i n t e rf a c e ) c o m p a t i b l e po r t . ext e rn al b u s pa c k i n g a n d un p a c k in g o f 16 -, 32-, 48-, o r 64-b i t w o r d s in in ter n al m e m o r y is p e r f o r m e d d u r i n g d m a tra n s f ers f r o m ei th er 8-, 16-, o r 32- b i t wi de ext e r n a l m e m o r y . f o ur t e en channe ls o f d m a a r e
adsst-sharc-mel-100 rev. 0 | page 10 of 28 available on the sharc mel-100; two are shared between the spi interface and the link ports, eight via the serial ports, and four via the processors external port (for either host processor, other sharc mel-100s memory or i/o transfers). programs can be downloaded to the sharc mel-100 using dma transfers. asynchronous off-chip peripherals can control two dma channels using dma request/grant lines ( dmar 1C2, dmag 1C2). other dma features include interrupt generation upon completion of dma transfers, and dma chaining for automatic linked dma transfers. multiprocessing the sharc mel-100 offers powerful features tailored to multiprocessing dsp systems. the external port and link ports provide integrated glueless multiprocessing support. the external port supports a unified address space (see figure 5) that enables direct interprocessor accesses of each sharc mel- 100 processors internal memory-mapped (i/o processor) registers. all other internal memory can be indirectly accessed via dma transfers initiated through the programming of the iop dma parameter and control registers. distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six sharc mel-100 processors and a host processor. master processor changeover incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotating priority. bus lock enables indivisible read-modify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. the maximum throughput for interprocessor data transfers is 400 mbytes/s over the external port. two link ports provide a second method of multiprocessing communications. each link port can support communications to another sharc mel-100. the sharc mel-100 running at 100 mhz has a maximum throughput for interprocessor communications over the links of 200 mbytes/s. the link ports and cluster multiprocessing can be used concurrently or independently. link ports the sharc mel-100 features two 8-bit link ports that provide additional i/o capabilities. with the capability of running at 100 mhz, each link port can support 100 mbytes/s. link port i/o is especially useful for point-to-point interprocessor communication in multiprocessing systems. the link ports can operate independently and simultaneously, with a maximum data throughput of 200 mbytes/s. link port data is packed into 48- or 32-bit words and can be directly read by the core processor, or dma-transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port transfers. transfers are programmable as either transmit or receive. serial ports the sharc mel-100 features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. each serial port is made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive. the serial ports operate at up to half the clock rate of the core, providing each with a maximum data rate of 50 mbps. the serial data pins are programmable as either a transmitter or receiver, providing greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via a dedicated dma. each of the serial ports features a time division multiplex (tdm) multichannel mode; two serial ports are tdm transmitters and two serial ports are tdm receivers (sport0 rx paired with sport2 tx, sport1 rx paired with sport3 tx). each of the serial ports also supports the i 2 s protocol (an industry-standard interface commonly used by audio codecs, adcs, and dacs), with two data pins, enabling four i 2 s channels (using two i 2 s stereo devices) per serial port, up to a maximum of 16 i 2 s channels. the serial ports enable little-endian or big-endian transmission formats and word lengths selectable from three bits to 32 bits. for i 2 s mode, data-word lengths are selectable between eight bits and 32 bits. serial ports offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. serial peripheral (compatible) interface serial peripheral interface (spi) is an industry-standard synchronous serial link, enabling the sharc mel-100 spi compatible port to communicate with other spi compatible devices. spi is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, supporting both master and slave modes. the spi port can operate in a multimaster environment by interfacing with up to four other spi compatible devices, acting as either a master or slave device. the sharc mel-100 spi compatible peripheral implementation also features programmable baud rate and clock phase/polarities. the sharc mel-100 spi compatible port uses open-drain drivers to support a multimaster configuration and to avoid data contention. host processor interface the sharc mel-100 host interface enables easy connection to standard 8-bit, 16-bit, or 32-bit microprocessor buses with little additional hardware required. the host interface is accessed through the sharc mel-100s external port. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the sharc mel-100s external bus with the host bus request ( hbr ), host bus grant ( hbg ), and ready (redy) signals. the host can directly read and write the internal iop registers of the sharc mel-100, and can access the dma channel setup and message registers. dma setup via a host would enable it to access any internal memory address via
adsst-sh arc-mel-100 rev. 0 | page 11 of 28 d m a t r a n sfers. v e c t o r in t e r r u p t s u p p o r t p r o v i d es ef f i cien t exe c u t io n o f h o st co mmands. general-p u rpose i/o ports the s h ar c m e l-100 als o co n t a i n s 12 p r og ra mma b l e , g e n e ra l- p u r p os e i/o p i ns tha t c a n f u n c tio n as ei ther in p u ts o r o u t p u t s. a s o u t p u t s, th es e p i n s ca n sig n a l p e r i p h eral de v i ces; as in p u ts, t h es e pin s ca n pr o v ide t h e t e s t fo r co n d i t io nal b r a n chi n g. program booting the in t e r n al m e m o r y o f th e s h ar c m e l - 100 c a n be bo o t e d a t sys t em p o w e r - up f r o m ei t h er an 8- b i t e p r o m, a h o s t p r o c es s o r , t h e spi i n te r f a c e, or t h rou g h on e of t h e l i n k p o r t s . s e l e c t i o n of th e bo o t s o ur ce is co n t r o l l ed b y th e b o ot m e m o r y s e lec t ( bms ), e b oo t ( e p r o m bo o t ) , a n d l i n k / h o s t bo o t ( l boo t ) p i n s . 8-, 16-, o r 32-b i t h o s t p r o c ess o rs ca n als o be us e d f o r bo o t in g. phas e d -loc ke d loop an d c r ys tal do ubl e e n a b le the s h ar c m e l-100 us es a n on-c hi p p h as e-lo c k e d lo o p (p ll) to ge ne r a te t h e i n te r n a l cl o c k for t h e c o re. t h e c l k _ c f g [ 1 : 0 ] p i n s a r e us e d t o s e lec t ra tios o f 2:1, 3:1, a n d 4:1. i n addi tion t o th e pl l ra ti os, t h e clkd bl p i n ca n b e u s e d fo r m o r e clo c k ra ti o o p ti o n s. th e (1/ 2 c l k i n ) ra t e se t b y th e clkd bl pi n det e r m i n es t h e ra t e o f t h e p ll i n p u t clo c k an d t h e r a t e a t w h ich t h e sy n c hr o n o u s ext e r n al p o r t o p era t es. w i t h t h e com b ina t ion o f clk_cfg[1: 0] a n d clkd bl , ra tios o f 2:1, 3:1, 4:1, 6: 1, a n d 8:1 betw een t h e co r e a nd cl ki n a r e s u p p o r t e d . s e e f i gur e 13. power supplies the s h ar c m e l-100 has s e p a ra t e p o w e r s u p p ly co nn ec tion s fo r t h e in ter n a l ( v ddint ), ext e r n al (v ddext ) , and an a l o g (a v dd /a gnd) p o w e r s u p p lies. the in t e r n al and a n alog s u p p lies m u s t m e et t h e 1.8 v r e q u ir emen t. th e ext e r n al su p p l y m u s t me e t t h e 3 . 3 v re qu ire m e n t. a l l e x te r n a l su p p ly p i ns m u st b e c o nne c t e d to t h e s a me su p p ly . n o te t h a t t h e an a l o g su p p ly ( a v dd ) p o w e rs th e s h ar c m e l-100 p r oc e s so r s c l oc k g e n e r a t o r p l l. t o p r od u c e a s t a b l e c l oc k , p r o v ide an ext e r n al cir c ui t t o f i l t er t h e p o w e r in p u t t o t h e a v dd p i n. p l ace t h e f i l t er as clos e as p o s s i b le t o t h e p i n. f o r a n exa m ple cir c ui t, s e e f i gur e 7. t o p r e v en t n o is e c o u p lin g , us e a w i de tra c e f o r th e a n alog gr o u n d (a gn d) si gnal a n d i n s t all a deco u p lin g ca p a ci t o r as c l os e as p o s s i b le t o th e p i n. v ddint 10 ? 0.1 f 0.01 f agnd av dd f i gure 7. a n a l og p o w e r (a v dd ) f i l t er circui t ack oe addr data cs we cont rol adsp-21161 #1 addr23 ? 0 control adsp-21161 #3 id2 ? 0 reset clkin 3 adsp-21161 #4 clock addr data sdram (optional) cs addr data id2 ? 0 reset clkin cont rol addre s s dat a cont rol addre s s dat a control adsp-21161 #2 id2 ? 0 reset clkin 2 1 addr data we ras cas dqm clk a10 cke cs data47 ? 16 sdwe ras cas dqm sdclk[1 ? 0] sda10 sdcke br6 ? 2 rd ms3 ? 0 sbts cs ack br1 redy hbg hbr wr bms addr23 ? 0 reset data47 ? 16 addr23 ? 0 data47 ? 16 boot eprom (optional) global memory and peripherals (optional) host processor interface (optional) f i gure 8. sh ared m e m o r y mult iprocessing s y stem
adsst-sh arc-mel-100 rev. 0 | page 12 of 28 pin function descriptions the s h ar c m e l-100 p i n def i ni tio n s ca n be f o un d in t a b l e 2 beg i nnin g o n p a g e 13. i n p u ts iden tif i e d as s y nc hr o n o u s (s) m u s t m e e t t i m i n g r e q u i r em e n ts wi th r e s p ec t t o c l k i n (o r w i th r e s p ec t t o t c k f o r t m s, td i). i n p u ts iden tif i e d as asy n chr o n o us (a) ca n b e ass e r t e d as y n chr o n o u sly t o clki n (o r to tc k for trst ). t i e o r p u l l un us ed in p u ts t o v ddex t or g n d , exc e p t fo r t h e fol l o w ing : ? ad d r 23C0, d a t a 47C0, b r s t , clk o ut . (n o t e tha t th es e p i n s ha v e a log i c le v e l h o ld cir c ui t enab le d o n t h e s h ar c m e l-10 0 ds p wi t h id2 C 0 = 00x.) ? pa , a c k , rd , wr , dm a r x , dm a g x , (id2C0 = 00x). (n o t e t h a t t h es e p i n s ha v e a p u l l - u p ena b le d o n t h e s h ar c m e l-10 0 ds p wi t h id2 C 0 = 00x.) ? lxclk, lxa c k, lxd a t7C0 (lxp d r d e = 0). (n o t e: s e e l i nk p o r t buf f er c o n t r o l reg i s t er bi t def i ni t i o n s in t h e s h ar c m e l-10 0 ds p h a rd wa re ref e r e n c e . ) ? d x a , d x b , s c l k x , s p i c l k , m i s o , m o s i , emu , tm s , trst , td i. (n o t e t h a t t h es e p i ns ha v e a p u l l -u p . ) t o p view 13 14 11 12 91 0 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd f i gure 9. jt a g t a r g et bo ar d con n ec to r for jt a g equ i p p e d a n al og d e v i ces ds p (ju m pers i n p l ace ) top vie w 13 14 11 12 91 0 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd f i gure 10. jt a g t a rget bo ar d con n ec tor with n o l o c a l b o undar y s c a n 0. 24" 0. 88" 0. 6 4 " f i gure 11. jt a g p o d c o nn ec tor d i me nsions 0.10" 0.15" f i gure 12. jt a g p o d conn ec tor k e ep - o ut a r ea the fol l o w in g s y m b ols a p p e a r i n t h e t y p e col u mn o f t a b l e 2: a asynchronous, g ground, i input, o output, p power supply, s synchronous, (a/d) active drive, (o/ d ) open drain, t three-state (when sbts is asserted or when the sharc mel-100 is a bus slave). u n li k e p r e v io us s h ar c p r o c ess o rs, th e s h arc m e l-100 co n t a i n s in t e r n al s e r i es r e sis t a n ce eq ui valen t t o 50 ? o n al l in p u t/o u t p ut dr i v ers excep t t h e clki n an d xt al p i n s . ther efo r e , fo r t r aces lo n g er t h a n six i n ch es, ext e r n al s e r i es re s i stor s on c o n t ro l, d a t a , cl o c k , or f r ame s y nc pi ns are not r e q u ir e d t o dam p en r e f l e c tio n s f r o m tra n smis sio n lin e ef fe c t s f o r p o i n t - to - p oi n t c o n n e c t i ons . h o we ve r , f o r more c o m p l e x n e tw o r ks such a s st a r co nf igura t io n s , s e r i es t e r m ina t ion is st i l l r e co mme n d e d .
sharc ? mel-100 audio processor adsst-sharc-mel-100 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. table 2. pin function description mnemonic type function ack i/o/s memory acknowledge . external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers , or other peripherals to hold off completion of an external memory access. the sharc mel-100 deasserts ack as an output to add wait states to a synchronous access of its iop registers. ack has a 20 k? internal pull -up resistor that is enabled during reset or on dsps with id2C0 = 00x. addr23C0 i/o/t external bus address . the sharc mel-100 outputs addresses for ex ternal memory and peripherals on these pins. in a multiprocessor system, the bus master outp uts addresses for read/writes of the iop registers of other sharc mel-100 processors, while all other internal memory resources can be accessed indirectly via dma control (that is, accessing iop dma parameter registers). the sharc mel-100 inputs addresses when a host processor or multiprocessing bus master is readin g or writing its iop registers. a keeper latch on the dsps addr23C0 pins maintains the input at the level to which it was last driven. this latch is only enabled on the sharc mel-100 with id2C0 = 00x. agnd g analog power supply return . av dd p analog power supply . nominally +1.8 v dc and supplies the dsp s internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitr y is required. see the power supplies section. bms i/o/t boot memory select . serves as an output or input as selected with the eboot and lboot pins; see table 3 on page 17. this input is a system configuration sele ction that should be hardwired. for host and eprom boot, dma channel 10 (epb0) is used. for link boot and spi boot, dma channel 8 is used. three-state only in eprom boot mode (when bms is an output). bmstr o bus master output . in a multiprocessor system, indicates whet her the sharc mel-100 is current bus master of the shared external bus. the sharc mel-100 drives bmst r high only while it is the bus master. in a single- processor system (id = 000), the processor drives this pin high. br 6C1 i/o/s multiprocessing bus requests . used by multiprocessing sharc mel-100 processors to arbitrate for bus mastership. a sharc mel-100 only drives its own br x line (corresponding to the value of its id2C0 inputs) and monitors all others. in a multiprocessor system with less than six sharc mel-100 processors, the unused br x pins should be pulled high; the processors own br x line must not be pulled high or low because it is an output. brst i/o/t sequential burst access . brst is asserted by sharc mel-100 to indicate that data associated with consecutive addresses is being read or written. a slave device samples the initial address and increments an internal address counter after each transfer. the incremented address is not pipelined on the bus. a master sharc mel-100 in a multiprocessor environment can read slave external port buffers (epbx) using the burst protocol. brst is asserted after the initial access of a burst transfer. it is asserted for every cycle after that, except for the last data request cycle (denoted by rd or wr asserted and brst negated). a keeper latch on the dsps brst pin maintains the input at the level to which it was last driven. this latch is only enabled on the sharc mel-100 with id2C0 = 00x. cas i/o/t sdram column access strobe . in conjunction with ras , ms x, sdwe , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. clk_cfg1C0 i core/clkin ratio control . sharc mel-100 core clock (instruc tion cycle) rate is equal to n plliclk where n is user selectable to 2, 3, or 4, using the clk_cfg1C0 inputs. these pins can also be used in combination with the clkdbl pin to generate additional core clock rates of 6 clkin and 8 clkin (see the clock rate ratios table in the clkdbl description).
adsst-sharc-mel-100 rev. 0 | page 14 of 28 clkdbl i crystal double mode enable . this pin is used to enable the 2 cloc k double circuitry, where clkout can be configured as either 1 or 2 the rate of clkin. this clkin double circuit is primarily intended to be used for an external crystal in conjunction with the internal clock generator an d the xtal pin. the internal clock generator, when used in conjunction wi th the xtal pin and an external crysta l, is designed to support up to a maximum of 25 mhz external crystal frequency. clkdbl can be used in xtal mode to generate a 50 mhz input into the pll. the 2 clock mode is enabled (during reset low) by tying clkdbl to gnd, otherwise it is connected to v ddext for 1 clock mode. for example, this enab les the use of a 25 mhz crystal to enable 100 mhz core clock rates and a 50 mhz clkout ope ration when clk_cfg1= 0, clk_cfg1= 0, and clkdbl = 0. this pin can also be used to generate different clock rate ratios for external clock oscillators. the possible clock rate ratio options (up to 100 mhz) for eith er clkin (external clock oscillator) or xtal (crystal input) are as follows: clock rate ratios clkdbl clk_cfg1 clk_cfg0 co re:clkin clkin:clkout 1 0 0 2:1 1 1 0 1 3:1 1 0 1 0 4:1 1 0 0 0 4:1 2 0 0 1 6:1 2 0 1 0 8:1 2 an 8:1 ratio enables the use of a 12.5 mhz crystal to generate a 100 mhz core (instruction clock) rate and a 25 mhz clkout (external port) clock rate. see figure 13. note that when using an external crystal, the maximum crystal freque ncy cannot exceed 25 mhz. for all other external clock sources, the maximum clkin frequency is 50 mhz. clkin i local clock in . used in conjunction with xtal. clkin is the sharc mel-100s clock input. it configures the sharc mel-100 to use either its internal clock gene rator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the sharc mel-100 to use the external clock source such as an external clock os cillator.the sharc mel-100 external port cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clkin frequency; it is programmable at power-up via the clk_cfg1C0 pins. clkin may not be halted, changed, or operated below the specified frequency. clkout o/t local clock out . clkout is 1 or 2 and is driven at either 1 or 2 the frequency of clkin frequency by the current bus master. the frequency is determined by the clkdbl pin. this output is three-stated when the sharc mel-100 is not the bus master or when the host controls the bus (hbg asserted). a keeper latch on the dsps clkout pin maintains the output at the level it was last driven. this latch is only enabled on the sharc mel-100 with id2C0 = 00x. if clkdbl enabled, clkout = 2 clkin if clkdbl disabled, clkout = 1 clkin note that clkout is controlled only by the clkdbl pin and operates at either 1 clkin or 2 clkin. do not use clkout in multiprocessing systems; use clkin instead. cs i/a chip select . asserted by host processor to select the sharc mel-100. data47C16 i/o/t external bus data . the sharc mel-100 inputs and outputs data and instructio ns on these pins. pull-up resistors on unused data pins are not necessary. a keeper latch on th e dsps data47C16 pins maintains the input at the level to which it was last driven. this latch is only enabled on the sharc mel-100 with id2C0 = 00x. note that data[15:8] pins (multiplexed with l1data[7:0]) can also be used to extend the data bus if the link ports are disabled and will not be used. in addition, da ta[7:0] pins (multiplexed with l0data[7:0]) can also be used to extend the data bus if the link ports are not used. this enables execution of 48-bit instructions from external sbsram (system clock speed-external port), sram (system clock speed-external port), and sdram (core clock or one-half the core clock speed). the ipackx instruction packing mode bits in syscon should be set correctly (ipack1C0 = 0x1) to enable this full instruction width/no-packing mode of operation. dmag1 o/t dma grant 1 (dma channel 11). asserted by sharc mel-100 to indicate that the requested dma starts on the next cycle. driven by bus master only. dmag1 has a 20 k? internal pull-up resistor that is enabled for dsps with id2C0 = 00x. dmag2 o/t dma grant 2 (dma channel 12). asserted by the sharc mel-1 00 to indicate that the requested dma starts on the next cycle. driven by the bus master only. dmag2 has a 20 k? internal pull-up resistor that is enabled for dsps with id2C0 = 00x.
adsst-sharc-mel-100 rev. 0 | page 15 of 28 dmar1 i/a dma request 1 (dma channel 11). asserted by external por t devices to request dma services. dmar1 has a 20 k? internal pull-up resistor that is enabled for dsps with id2C0 = 00x. dmar2 i/a dma request 2 (dma channel 12). asserted by external port devices to request dma services. dmar2 has a 20 k? internal pull-up resistor that is enabled for dsps with id2C0 = 00x. dqm o/t sdram data mask . in write mode, dqm has a latency of zero and is used during a precharge command and during sdram power-up initialization. dxa i/o data transmit or receive channel a (serial ports 0, 1, 2, 3). each dxa pin has an internal pull-up resistor. bidirectional data pin. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. dxb i/o data transmit or receive channel b (serial ports 0, 1, 2, 3). each dxb pin has an internal pull-up resistor. bidirectional data pin. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. eboot i eprom boot select . for a description of how this pin operates, see table 3 on page 17. this signal is a system configuration selection that should be hardwired. emu (o/d) emulation status . must be connected to the sharc mel-100 analog devices dsp tools product line of jtag emulators target board connector only. emu has an internal pull-up resistor. flag11C0 i/o/a flag pins . each pin is configured via control bits as either an input or output. as an inp ut, it can be tested as a condition. as an output, it can be us ed to signal external peripherals. fsx i/o transmit or receive frame sync (serial ports 0, 1, 2, 3). the frame sync pulse initiates shifting of serial data. this signal is either genera ted internally or externally. it can be active high or low or an early or late frame sync, in reference to the shifting of serial data. gnd g power supply return (26 pins). hbg i/o host bus grant . acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the sharc mel-100 until hbr is released. in a multiprocessing system, hbg is output by the sharc mel-100 bus master and is monitored by all others. after hbr is asserted, and before hbg is given, hbg will float for 1 t ck (1 clkin cycle). to avoid erroneous grants, hbg should be pulled up with a 20 k? to 50 k? external resistor. hbr i/a host bus request . must be asserted by a host processor to re quest control of the sharc mel-100 processors external bus. when hbr is asserted in a multipro cessing system, the sharc mel-100 that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the sharc me l-100 places the address, data, select, and strobe lines in a high impedance state. hbr has priority over all sharc mel-100 bus requests (br 6C1) in a multiprocessing system. id2C0 i multiprocessing id . determines which multiprocessing bus request (br 6C1) is used by the sharc mel-100. id = 001 corresponds to br1 , id = 010 corresponds to br2 , and so on. use id = 000 or id = 001 in single- processor systems. these lines are a system configuration selection that should be hardwired or only changed at reset. irq 2C0 i/a interrupt request lines . these pins are sampled on the rising edge of clkin and may be either edge- triggered or level-sensitive. lboot i link boot . for a description of how this pin operates, see table 3 on page 17. this signal is a system configuration selection that should be hardwired. lxack i/o link port acknowledge (link ports 0C1). each lxack pin has an in ternal pull-down 50 k? resistor that is enabled or disabled by the lxpd rde bit of the lctl register. lxclk i/o link port clock (link ports 0C1). each lxclk pin has an internal pull-down 50 k? resistor that is enabled or disabled by the lxpdrde bit of the lctl register. lxdat7C0 [data15C0] i/o [i/o/t] link port data (link ports 0C1). for silicon revisions 1.2 and higher, each lxdat pin has a keeper latch that is enabled when used as a data pin, or a 20 k? internal pull-down resistor that is enable d or disabled by the lxpdrde bit of the lctl register. for silicon revisions 0.3, 1.0, and 1.1, each lxdat pin ha s a 50 k? internal pull-down resistor that is enabled or disabled by the lxpdrde bit of the lctl register. note that l1data[7:0] are multiplexed with the data [15:8] pins; l0data[7:0] are multiplexed with the data[7:0] pins. if link ports are disabled and are not be used, these pins can be used as additional data lines for executing instructions at up to the full clock rate from external memory. see data47C16 for more information.
adsst-sharc-mel-100 rev. 0 | page 16 of 28 miso i/o (o/d) spi master in slave out . if the sharc mel-100 is configured as a master, the miso pin becomes a data receive (input) pin. if the sharc mel-100 is configured as a slave, the miso pin becomes a data transmit (output) pin. in a sharc mel-100 spi interconnection, th e data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the master. miso has an inte rnal pull-up resistor. miso can be configured as o/d by setting the opd bit in the spictl register. note that only one slave is enabled to transmit data at any given time. mosi i/o (o/d) spi master out slave . if the sharc mel-100 is configured as a ma ster, the mosi pin becomes a data transmit (output) pin. if the sharc mel-100 is configured as a slave, the mosi pin becomes a data receive (input) pin. in asharc mel-100 spi interconnection, the data is shif ted out from the mosi outp ut pin of the master and shifted into the mosi input(s) of the slave( s). mosi has an internal pull-up resistor. ms 3C0 i/o/t memory select lines . these outputs are asserted (low) as chip selects for the corresponding banks of external memory. memory bank sizes are fixed to 16 mwords for non-sdram and 64 mwords for sdram. the ms 3C0 outputs are decoded memory address line s. in asynchronous access mode, the ms 3C0 outputs transition with the other address outp uts. in synchronous access modes, the ms 3C0 outputs assert with the other address lines; however, they de-assert after the fi rst clkin cycle in which ack is sampled asserted. in a multiprocessor systems, the ms x signals are tracked by slave sharcs. the internal addresses 24 and 26 are zeros and 26 and 27 are decoded into ms 3C0. nc do not connect . reserved pins that must be left open and unconnected (5 pins). pa i/o/t priority access . asserting its pa pin enables a sharc mel-100 bus slave to interrupt background dma transfers and gain access to the external bus. pa is connected to all sharc mel-100 processors in the system. if access priority is not required in a system, pa should be left unconnected. pa has a 20 k? internal pull-up resistor that is enabled for dsps with id2C0 = 00x. ras i/o/t sdram row access strobe . in conjunction with cas , ms x, sdwe , sdclkx, and sometimes sda10, this pin defines the operation for the sdram to perform. rd i/o/t memory read strobe . rd is asserted whenever the sharc mel-100 reads a word from external memory or from the iop registers of other sharc mel-100 processo rs. external devices, including other sharc mel-100 processors, must assert rd for reading a word of the sharc mel-100 iop register memory. in a multiprocessing system, rd is driven by the bus master. rd has a 20 k? internal pull-up resistor that is enabled for dsps with id2C0 = 00x. redy o (o/d) host bus acknowledge . the sharc mel-100 deasserts redy (low) to a dd wait states to a host access of its iop registers when cs and hbr inputs are asserted. reset i/a processor reset . resets the sharc mel-100 to a known state an d begins execution at the program memory location specified by the hardware reset vector address. the reset input must be asserted (low) at power-up. rpba i/s rotating priority bus arbitration select . when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configuration selection that must be set to the same value on every sharc mel-100. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every sharc mel-100. rstout o reset out . when rstout is asserted (low), this pin in dicates that the core blocks ar e in reset. it is deasserted 4096 cycles after reset is deasserted indicating that th e pll is stable and locked. (rstout exists only for silicon revision 1.2.) sbts i/s suspend bus and three-state . external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. if the sharc mel-100 attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recover from host processor/sharc mel-100 deadlock. sclkx i/o transmit/receive serial clock (serial ports 0, 1, 2, 3). each sclk pi n has an internal pull-up resistor. this signal can be either internally or externally generated. sda10 o/t sdram a10 pin . enables applications to refresh an sdram in parallel with a non-sdram accesses or host accesses. sdclk0 i/o/s/t sdram clock output 0. clock for sdram devices. sdclk1 o/s/t sdram clock output 1 . additional clock for sdram devices. for sy stems with multiple sdram devices, this pin handles the increased clock load requirements, el iminating the need for off-chip clock buffers. either sdclk1 or both sdclkx pins can be three-stated. sdcke i/o/t sdram clock enable . enables and disables the clk signal. for details, see the data sheet supplied with the sdram device. sdwe i/o/t sdram write enable . in conjunction with cas , ras , ms x, sdclkx, and sometimes sda10, this pin defines the operation for the sdram to perform.
adsst-sharc-mel-100 rev. 0 | page 17 of 28 spiclk i/o serial peripheral interface clock signal . driven by the master, this signal controls the rate at which data is transferred. the master may transmit data at a variety of baud rates. spiclk cycles once for each bit trans mitted. spiclk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devices igno re the serial clock if the slave select input is driven inactive (high). spiclk is used to shif t out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge of the clock and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programma ble into the spictl control register and define the transfer format. spiclk has an internal pull-up resistor. spids i serial peripheral interface slave device select . an active low signal used to enable slave devices. this input signal behaves like a chip select, and is prov ided by the master device for the slave devices. in multimaster mode, the spids signal can be asserted to a master device to signal that an error has occurred because some other device is also tryi ng to be the master device. if assert ed low when the device is in master mode, it is considered a multimaster error. for a si ngle-master, multiple-slave configuration where flag3C0 are used, this pin must be tied or pulled high to v ddext on the master device. for sharc mel-100 to sharc mel-100 spi interaction, any of the master sharc mel-100 processors flag3C0 pins can be used to drive the spids signal on the sharc mel-100 spi slave device. tck i test clock (jtag). provides a clock for jtag boundary scan. tdi i/s test data input (jtag). provides serial data for the boundary scan logic. tdi has a 20 k? internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. timexp o timer expired . asserted for four core clock cy cles when the timer is enabled. tms i/s test mode select (jtag). used to control the test state machine. tms has a 20 k? internal pull-up resistor. trst i/a test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the sharc mel-100. trst has a 20 k? internal pull-up resistor. v ddint p core power supply . nominally 1.8 v dc and supplies the dsps core processor (14 pins). v ddext p i/o power supply . nominally 3.3 v dc (13 pins). wr i/o/t memory write low strobe . wr is asserted when the sharc mel-100 wr ites a word to external memory or iop registers of other sharc mel-100 proce ssors. external devices must assert wr for writing to the sharc mel-100s iop registers. in a multiprocessing system, wr is driven by the bus master. wr has a 20 k? internal pull-up resistor that is enabled for dsps with id2C0 = 00x. xtal o crystal oscillator terminal 2 . used in conjunction with clkin to en able the sharc mel-100s internal clock oscillator or to disable it to use an external clock source. see clkin. boot modes table 3. boot mode selection eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select). 0 0 1 (input) host processor. 0 1 0 (input) serial boot via spi. 0 1 1 (input) link port. 0 0 0 (input) no booting. proc essor executes from external memory. 1 1 x (input) reserved.
adsst-sharc-mel-100 rev. 0 | page 18 of 28 specifications recommended operating conditions table 4. c grade k grade parameter test conditions min max min max unit v ddint internal (core) supply voltage 1.71 1.89 1.71 1.89 v av dd analog (pll) supply voltage 1.71 1.89 1.71 1.89 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v ih high level input voltage 2 @ v ddext = max 2.0 v ddext + 0.5 2.0 v ddext + 0.5 v v il low level input voltage 2 @ v ddext = min C0.5 0.8 C0.5 0.8 v t case case operating temperature 3 C40 +105 0 +85 c 2 applies to input and bidirectio nal pins: data47 C16, addr23C0, ms 3C0, rd , wr , ack, sbts , irq2C0, flag11C0, hbg , hbr , cs , dmar1 , dmar2 , br 6C1, id2C0, rpba, pa , brst, fsx, dxa, dxb, sclkx, ras , cas , sdwe , sdclk0, lxdat7C0, lxclk, lxack, spiclk, mosi, miso, spids , eboot, lboot, bms , sdcke, clk_cfgx, clkdbl , clkin, reset , trst, tck, tms, tdi. 3 see the thermal characteristics section on page 23 for informat ion on thermal specifications.
adsst-sharc-mel-100 rev. 0 | page 19 of 28 electrical characteristics table 5. parameter test conditions min max unit v oh high level output voltage 4 @ v ddext = min, i oh = C2.0 ma 5 2.4 v v ol low level output voltage 4 @ v ddext = min, i ol = 4.0 ma 5 0.4 v i ih high level input current 6 , 7 @ v ddext = max, v in = v ddext max 10 a i il low level input current 6 @ v ddext = max, v in = 0 v 10 a i ihc clkin high level input current 8 @ v ddext = max, v in = v ddext max 25 a i ilc clkin low level input current 8 @ v ddext = max, v in = 0 v 25 a i ikh keeper high load current 9 @ v ddext = max, v in = 2.0 v C250 C100 a i ikl keeper low load current 9 @ v ddext = max, v in = 0.8 v 50 200 a i ikh-od keeper high overdrive current 9 , , 10 11 @ v ddext = max C300 a i ikl-od keeper low overdrive current 9 , 10 , 11 @ v ddext = max 300 a i ilpu low level input current pull-up 7 @ v ddext = max, v in = 0 v 250 a i ozh three-state leakage current 12 , , 13 14 @ v ddext = max, v in = v ddext max 10 a i ozl three-state leakage current 12 , 12, 13 @ v ddext = max, v in = 0 v 10 a i ozlpu1 three-state leakage current pull-up1 13 @ v ddext = max, v in = 0 v 500 a i ozlpu2 three-state leakage current pull-up2 14 @ v ddext = max, v in = 0 v 250 a i ozhpd1 three-state leakage current pull-down1 15 @ v ddext = max, v in = v ddext max 250 a i ozhpd2 three-state leakage current pull-down2 16 @ v ddext = max, v in = v ddext max 500 a i dd-inpeak supply current (internal) 17 , 18 t cclk = 10.0 ns, v ddint = max 900 ma i dd-inhigh supply current (internal) 18 , 19 t cclk = 10.0 ns, v ddint = max 650 ma i dd-inlow supply current (internal) 18 , 20 t cclk = 10.0 ns, v ddint = max 500 ma i dd-idle supply current (idle) 18 , 21 t cclk = 10.0 ns, v ddint = max 400 ma ai dd supply current (analog) 22 @av dd = max 10 ma c in input capacitance 23 , 24 f in = 1 mhz, t case = 25c, v in = 1.8 v 4.7 pf 4 applies to output and bidirect ional pins: data47 C16, addr23C0, ms 3C0, rd , wr , ack, dqm, flag11C0, hbg , redy, dmag1 , dmag2 , br 6C1, bmstr, pa , brst, fsx, dxa, dxb, sclkx, ras , cas , sdwe , sda10, lxdat7C0, lxclk, lxack, spiclk, mosi, miso, bms , sdclkx, sdcke, emu , xtal, tdo, clkout, timexp, rstout . 5 see the output drive currents section on page 21 for typical drive current capabilities. 6 applies to input pins : data47C16, addr23C0, ms 3C0, sbts , irq2C0, flag11C0, hbg , hbr , cs , br 6C1, id2C0, rpba, brst, fsx, dxa, dxb, sclkx, ras , cas , sdwe , sdclk0, lxdat7C0, lxclk, lxack, spiclk, mosi, miso, spids , eboot, lboot, bms , sdcke, clk_cfgx, clkdbl , tck, reset , clkin. 7 applies to input pins with 20 k? internal pull-ups: rd , wr , ack, dmar1 , dmar2 , pa , trst, tms, tdi. 8 applies to clkin only. 9 applies to all pins with keeper latches: addr23C0, data47C0, ms 3C0, brst, clkout. 10 current required to switch from kept high to low or from kept low to high. 11 characterized, but not tested. 12 applies to three-statable pins: data47C 16, addr23C0, ms 3C0, clkout, flag11C0, redy, hbg , bms , br 6-1, ras , cas , sdwe , dqm, sdclkx, sdcke, sda10, brst. 13 applies to three-statable pins with 20 k? pull-ups: rd , wr , dmag1 , dmag2 , pa . 14 applies to three-statable pins with 50 k? internal pull-ups: dxa, dxb, sclkx, spiclk, emu , miso, mosi. 15 applies to three-statable pins with 50 k? internal pull-downs: lxdat7C0 (below revision1.2), lxclk, lxack. use i ozhpd2 for rev. 1.2 and higher. 16 applies to three-statable pins with 20 k? internal pull-downs: lxdat7C0 (revision 1.2 and higher). 17 the test program used to measure i dd-inpeak represents worst-case processor operatio n and is not sustainable under normal a pplication conditions . actual internal power measurements made using typical applicat ions are less than specified. for more information, see the power dissipation sec tion on page 21. 18 current numbers are for v ddint and av dd supplies combined. 19 i dd-inhigh is a composite average based on a range of high activi ty code. see the power dissipation section on page 21. 20 i dd-inlow is a composite average based on a range of low activity code. see the power dissipation section on page 21. 21 idle denotes sh arc mel-100 state during execution of idle instruction. see the power dissipation section on page 21. 22 characterized, but not tested. 23 applies to all signal pins. 24 guaranteed, but not tested.
adsst-sh arc-mel-100 rev. 0 | page 20 of 28 absolute maximum ra tings table 6. p a r a m e t e r r a t i n g internal (core) supply voltage (v ddin t ) C0.3 v to +2.2 v analog (pll) su pply voltage (av dd ) C0.3 v to +2.2 v ex ternal (i/ o ) suppl y vol t age (v ddex t ) C0.3 v to +4.6 v input voltage C0.5 v to v ddex t + 0.5 v output voltage swing C0.5 v to v ddex t + 0.5 v load capacitance 200 pf storage temperature range C65c to +150c s t r e s s es g r e a t e r t h a n t h os e lis t e d a b o v e ma y c a us e p e r m a n e n t da ma g e t o t h e de v i ce . th es e a r e s t r e s s ra t i n g s on l y ; f u n c t i o n al op e r a t i o n of t h e d e v i c e a t t h e s e or an y ot he r c o nd it i o n s g r e a te r t h a n t h o s e i n di c a te d i n t h e o p er a t io na l s e c t io n s o f t h is sp e c if ic a t ion is n o t i m plie d . e x p o sur e t o a b s o lu t e maxi m u m r a t i n g condi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vic e rel i a b i l it y . timing spe c ific a t ions the s h ar c m e l-100 p r o c ess o r s in t e r n al c l o c k s w i t c h es a t hig h er f r e q uen c ies t h a n t h e sys t em i n p u t clo c k (clkin). t o g e n e r a t e t h e in ter n al clo c k, t h e p r o c es s o r us es a n in t e r n al phas e-lo ck e d lo o p (p ll). this p ll bas e d c l o c kin g minimizes th e sk e w be tw e e n t h e sys t e m c l o c k (clki n ) sig n al a nd t h e p r oc e s so r s in t e rn al c l oc k ( t h e c l oc k so u r c e f o r th e e x t e rn al po r t lo g i c a n d i/ o p a ds). the s h ar c m e l-100 p r o c ess o r s in t e r n al c l o c k (a m u l t i p le o f clki n) p r o v ides t h e clo c k sig n al fo r t i min g i n t e r n al m e m o r y , p r oc e s so r c o r e , l i nk po r t s , se ri al po r t s , a n d e x t e rn al po r t ( a s re qu i r e d f o r re a d / w r i te st ro b e s i n a s y n ch ronou s a c c e ss mo d e ) . du ri n g r e se t , p r o g r a m th e ra ti o bet w een th e p r o c e s so r s i n t e rn al c l oc k f r eq ue n c y a n d e x t e rn al (cl k in ) c l ock f r eq ue n c y w i t h th e clk_cfg1 C0 and clkd bl p i n s . e v e n th o u gh th e i n t e rn a l clo c k is t h e clo c k s o ur ce fo r t h e ext e r n al p o r t , i t b e ha v e s as des c r i b e d on t h e c l o c k r a te r a t i o cha r t in clkd bl pi n des c r i p t io n in t a b l e 2. t o de ter m i n e s w i t chi n g f r e q uen c ies fo r t h e s e r i a l an d l i n k p o r t s, divi de do wn t h e i n ter n a l clo c k usin g th e p r ogra mmab l e d i vider co n t r o l o f eac h p o r t (d ivx f o r th e se ri al po r t s a n d l x c l k d f o r th e l i nk po r t s ) . ep: multiprocessing host sram sbsram ratios 2, 3, 4 link port: 1, 1/2, 1/3, 1/4 by sw core io-processor ep: sdram 1/2, 1 by sw clkout lclk[1:0] sdclk[1:0] cclk (33.3mhz to 100mhz) plliclk (8.4mhz? 50mhz) clk_cfg[1:0] clkdbl clkin (4.2mh z ? 50mhz) xtal quartz crystal or crystal oscillator clock doubler 1, 2 pll f i g u re 13. co r e c l o c k and sy s t em r e l a t i ons h ip t o clki n
adsst-sh arc-mel-100 rev. 0 | page 21 of 28 po wer diss ip a t ion t o tal p o w e r dissi p a tion has two co m p on e n ts: o n e d u e t o in t e r n al cir c ui t r y a n d one d u e to t h e s w i t chi n g o f ext e r n al o u t p ut dr i v ers. i n ter n a l p o w e r d i ssi p a t ion de p e n d s on t h e in st r u c t io n exe c u t io n s e q u e n ce a nd t h e da t a o p er a n ds in volve d . u s in g t h e c u r r e n t sp e c if ic a t io ns (i dd- inp e a k , i dd - i n h ig h , i dd- inl o w , i dd - i dle ) f r o m th e e l ec tr ical c h a r ac t e r i s t ics ( t a b le 5 o n p a g e 19), th e p r og ra mm er ca n es t i ma t e t h e s h arc m e l-100 p r o c es s o r s in t e r n a l p o w e r su p p ly (v ddint ) in p u t c u r r en t fo r a sp e c if ic a p plic a t ion, acc o r d in g t o t h e fol l o w in g fo r m u l a: i ddi n t = % pe a k i dd - i n p e a k + % hi g h i dd - i n h ig h + % lo w i dd - i nlo w + % id l e i dd - i dl e the ext e r n al com p on e n t o f t o t a l p o w e r dis s i p a t io n is c a us e d b y t h e s w itch i n g of output pi ns . i t s m a g n itu d e d e p e nd s o n ? the n u m b er o f o u t p u t p i n s tha t swi t ch d u r i n g e a c h c y c l e ( o ) ? the max i m u m f r e q uen c y a t w h ich t h e y can s w i t ch ( f ) ? their lo ad c a p a ci t a n c e ( c ) ? their v o l t a g e s w i n g ( v dd ) a nd is ca lc u l a t e d b y p ex t = o c v dd 2 f the lo ad c a p a ci t a nce sh o u ld i n cl ude t h e p r o c ess o r p a cka g e ca p a c i tan c e (c in ). th e s w i t ching f r e q uen c y in cl udes dr i v i n g t h e lo ad hig h and t h e n b a ck lo w . a ddr ess and d a t a p i n s c a n dr i v e hig h and lo w a t a max i m u m ra te o f 1/t ck wh ile w r i t in g t o a n sdr a m me mo r y . ex a m p l e : es tima te p ext wi th t h e f o llo w i n g a s s u m p ti o n s: ? a sys t em wi th on e b a n k o f ext e r n al m e m o r y (32 b i t) ? t w o 1m 16 s d ram c h i p s a r e us ed , eac h wi t h a lo ad o f 10 pf (ig n o r in g trace c a p a ci t a n c e) ? e x t e r n al da t a mem o r y wr i t es can o c c u r e v er y c y cle a t a ra t e o f 1/t ck , wi t h 50% o f the p i n s s w i t chin g ? the b u s c y c l e tim e is 50 m h z ? the ext e r n al s d ram c l o c k ra t e is 100 mh z ? s d r a m r e f r es h c y cles a r e ig n o r e d ? a ddr es s e s a r e i n cr e m en t a l and o n t h e s a m e p a g e the p ex t eq u a tio n is calc u l a t e d f o r eac h c l as s o f p i n s tha t can dr i ve.a ty p i ca l p o w e r co n s um pt io n can n o w b e ca lc u l a t e d fo r t h es e condi t i o n s b y addin g a ty p i ca l i n ter n a l p o w e r dissi p a t ion: p to t a l = p ex t + p int + p pl l w h er e p p ll is ai dd 1.8 v , usin g th e val u e f o r ai dd lis t ed in t h e e l ec tr ical cha r ac t e r i s t ics ( t a b le 5 o n p a g e 19). outpu t dri v e current s f i gur e 14 s h o w s typ i cal i - v c h arac t e r i s t ics f o r th e o u t p u t dr i v ers o f th e s h ar c m e l-100. the c u r v es r e p r es en t t h e c u r r en t dr i v e ca p a b i li ty o f t h e ou t p ut dr i v ers as a f u n c t i on o f out p ut vol t ag e. 60 ?10 50 0 ?20 30 10 40 20 load (v d d ext ) curre nt (ma) 70 ?30 ?40 ?50 ?60 ?70 source (v ddext ) voltage (v) 0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 4. 0 v ddext = 3.47v, ?40c v ddext = 3.3v, +25c v ddext = 3.13v, +105c v ddext = 3.13v, +105c v ddext = 3.3v, +25c v ddext = 3.47v, ?40c f i gure 14. t y pic a l d r ive cu rrents test c o n d i t io ns out p ut enabl e tim e ou t p u t p i n s a r e co n s i d e r ed t o b e e n a b l e d w h en th ey h a v e ma d e a tra n si ti o n f r o m a hi gh im p e da n c e s t a t e t o th e po i n t w h en th e y s t a r t dr i v in g. th e o u t p ut ena b l e t i m e , t en a , is t h e in ter v a l f r o m t h e p o i n t w h e n a re f e re nc e s i g n a l re a c he s a h i g h or l o w vo lt age le v e l t o t h e p o in t w h en t h e ou t p u t has r e ach e d a s p e c if ie d hig h o r lo w tr i p p o in t, as sh o w n in f i gur e 15. i f m u l t i p le p i n s (s uc h as t h e da t a b u s) a r e ena b le d , t h e m e as ur e m en t v a l u e is t h a t o f t h e f i rst pin t o st a r t dr i v i n g. out p ut disabl e tim e ou t p u t p i n s a r e co n s i d e r ed t o b e d i sa b l e d w h en th ey s t o p dr i v i n g, go in to a hig h im p e dance st a t e, and st ar t to de ca y f r o m t h eir o u t p u t hig h o r lo w v o l t a g e. th e t i m e fo r t h e v o l t a g e on t h e bu s t o d e c a y by ? v i s d e pen d e n t o n th e ca pa c i ti v e l o a d , c l , a nd t h e lo ad c u r r en t , i l . this de ca y t i me can b e a p p r o x ima t e d b y t h e eq ua ti o n l l decay i v c t ? = the o u t p u t dis a b l e t i m e , t dis , is t h e dif f er en ce b e tw e e n t meas ure d a nd t deca y , a s s h o w n i n f i g u r e 1 5 . t h e t i m e t meas ured is t h e in t e r v al f r o m w h e n t h e r e fer e n c e sig n al s w i t ch e s t o w h en t h e output vo lt ag e d e c a y s ? v f r om t h e me a s u r e d output h i g h or out p ut l o w vol t age. t deca y is calc u l a t e d wi t h t e st lo ads c l an d i l , a nd wi t h ?v eq ual t o 0.5 v .
adsst-sh arc-mel-100 rev. 0 | page 22 of 28 exampl e sys t em hol d ti me c a lc ulation t o deter m in e t h e da t a o u t p u t hold time in a p a r t ic u l a r sys t em, fi r s t c a l c u l a t e t de c a y usin g th e e q ua t i o n g i v e n p r evio us l y . c h o o s e ?v t o be t h e dif f er en ce betw een th e s h ar c m e l-100 p r o c es s o r s o u t p u t v o l t a g e an d t h e i n p u t t h r e shold fo r t h e de vi ce r e q u ir in g t h e hold t i me . a ty p i ca l ?v wi l l b e 0 . 4 v . c l is t h e t o tal b u s ca pa ci ta n c e ( p e r da ta l i n e ) a n d i l is t h e t o tal le aka g e o r t h r e e-s t a t e c u r r en t (p er da t a li ne). th e h o ld t i me wi l l b e t deca y pl us t h e mi ni m u m dis a b l e t i m e . reference signal t dis output starts driving v oh (measured) ? ? v t measured v oh (measured) 2.0v 1.0v v oh (measured) v ol (measured) output stops driving t ena t decay high-impedance state. test conditions cause this voltage to be approximately 1.5v. v ol (measured) + ? v v ol (measured) f i g u re 15. o u t p ut e n abl e /d is ab le 1.5 v to outpu t pin 50 ? 30pf f i g u re 16. equiv a le nt d e v i c e l o ad ing f o r a c m e as u r e m e n t s (incl u d e s al l f i x t u r es) input or output 1.5v 1.5v f i gure 17. v o ltage r e fer e n c e l e ve ls fo r a c me asurem ent s ( e x c ept o u t p ut e n able/d is ab le) c a p a citiv e lo ading o u t p u t dela y s and h o lds a r e b a s e d on st anda rd ca p a ci t i ve lo ad s: 30 pf o n al l p i ns (s ee f i gur e 16 ). f i gur e 18 s h o w s h o w o u t p u t d e la ys a n d h o lds v a r y w i th loa d ca pa ci ta n c e . (n o t e th a t th i s g r a p h o r der a t i n g do es n o t a p ply to o u t p u t dis a b l e dela y s ; s e e t h e o u t p ut dis a b l e t i m e s e c t ion.) th e g r a p h s o f f i gur e 18, f i gur e 19, a nd f i gur e 20 ma y n o t be linea r o u tside the ra n g es sh own fo r t y p i c a l o u t p ut d e la y vs. l o ad c a p a c i t a nce and t y p i cal o u t p u t r i s e /f al l t i m e ( 20%C80 % , v = m i n) vs. l o ad ca pa c i t a n c e . load capacitance (pf) 25 ?5 0 210 30 60 90 120 150 180 20 15 10 5 nominal y = 0.0835x ? 2.42 output delay or hold ( n s) f i g u re 18. t y pic a l o u t p ut d e l a y or h o ld v s . l oad cap a c i t a nc e (at max case t e m p er atu r e) load capacitance (pf) 16 8 0 0 200 20 40 60 80 100 120 140 160 180 14 12 4 2 10 6 fall time rise time y = 0.0743x + 1.5613 ris e and fall time s (ns ) ( 0 .694v to 2.77v, 20% to 80%) y = 0.0414x + 2.0128 f i g u re 19. t y pic a l o u t p ut r i s e /f a ll ti me ( 20% C 80% , v ddex t = m a x) load capacitance (pf) 16 8 0 0 200 20 40 60 80 100 120 140 160 180 14 12 4 2 10 6 fall time rise time y = 0.0773x + 1.4399 ris e and fall time s (ns ) ( 0 .694v to 2.77v, 20% to 80%) y = 0.0417x + 1.8674 f i g u re 20. t y pic a l o u t p ut r i s e /f a ll ti me ( 20% C 80% , v ddex t = m i n)
adsst-sharc-mel-100 rev. 0 | page 23 of 28 environmental conditions thermal characteristics the sharc mel-100 is packaged in a 225-lead mini ball grid array (mbga). the sharc mel-100 is specified for a case temperature (t case ). to ensure that the t case specification is not exceeded, a heat sink and/or an airflow source may be used. use the center block of ground pins (mbga balls: f6C10, g6C10, h6C10, j6C10, k6C10) to provide thermal pathways to the printed circuit boards ground plane. a heat sink should be attached to the ground plane with a thermal adhesive as close as possible to the thermal pathways. t case = t amb + ( pd ca ) where: t case = case temperature (measured on top surface of package) pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown in the power dissipation section on page 21). ca = value from table 7. table 7. airflow over package vs. ca airflow (linear ft/min) 0 200 400 ca (c/w) 25 17.9 15.2 13.7 25 jc = 6.8c/w.
adsst-sharc-mel-100 rev. 0 | page 24 of 28 pin configuration table 8. 225-lead metric mbga pin assignments pbga pin number mnemonic pbga pin number mnemonic pbga pin number mnemonic pbga pin number mnemonic pbga pin number mnemonic a01 nc d01 tdo g01 flag1 k01 timexp n01 addr[14] a02 bmstr d02 tck g02 flag2 k02 addr[22] n02 addr[15] a03 bms d03 flag11 g03 flag4 k03 addr[20] n03 addr[10] a04 spids d04 miso g04 flag3 k04 addr[23] n04 addr[5] a05 eboot d05 sclk0 g05 v ddext k05 v ddint n05 addr[1] a06 lboot d06 d1b g06 gnd k06 gnd n06 ms0 a07 sclk2 d07 fs1 g07 gnd k07 gnd n07 br5 a08 d3b d08 v ddint g08 gnd k08 gnd n08 br2 a09 l0dat[4] d09 sclk3 g 09 gnd k09 gnd n09 brst a10 l0ack d10 l0dat[5] g 10 gnd k10 gnd n10 sdcke a11 l0dat[2] d11 l0dat[3] g11 v ddext k11 v ddint n11 cs a12 l1dat[6] d12 l1dat[5] g12 data [34] k12 data[22] n12 clk_cfg1 a13 l1clk d13 data[42] g13 data[ 35] k13 data[19] n13 clk_cfg0 a14 l1dat[2] d14 data[46] g14 data[33] k14 data[21] n14 av dd a15 nc d15 data[44] g15 da ta[32] k15 data[23] n15 dmar1 b01 trst e01 flag10 h01 flag0 l01 addr[19] p01 addr[13] b02 tdi e02 reset h02 irq0 l02 addr[17] p02 addr[9] b03 rpba e03 flag8 h03 v ddint l03 addr[21] p03 addr[8] b04 mosi e04 d0a h04 irq1 l04 addr[2] p04 addr[4] b05 fs0 e05 v ddext h05 v ddint l05 v ddext p05 ms2 b06 sclk1 e06 v ddint h06 gnd l06 v ddint p06 sbts b07 d2b e07 v ddext h07 gnd l07 v ddext p07 br4 b08 d3a e08 v ddint h08 gnd l08 v ddint p08 br1 b09 l0dat[7] e09 v ddext h09 gnd l09 v ddext p09 sdclk1 b10 l0clk e10 v ddint h10 gnd l10 v ddint p10 sdclk0 b11 l0dat[1] e11 v ddext h11 v ddint l11 v ddext p11 redy b12 l1dat[4] e12 l0dat[ 0] h12 data[29] l12 cas p12 clkin b13 l1ack e13 data[39] h13 da ta[28] l13 data[20] p13 dqm b14 l1dat[0] e14 data[43] h14 da ta[30] l14 data[16] p14 agnd b15 rstout 26 e15 data[41] h15 data[ 31] l15 data[18] p15 dmar2 c01 tms f01 flag5 j01 irq2 m01 addr[16] r01 nc c02 emu f02 flag7 j02 id1 m02 ad dr[12] r02 addr[11] c03 gnd f03 flag9 j03 id2 m03 addr[18] r03 addr[7] c04 spiclk f04 flag6 j04 id0 m04 addr[6] r04 addr[3] c05 d0b f05 v ddint j05 v ddext m05 addr[0] r05 ms3 c06 d1a f06 gnd j06 gnd m06 ms1 r06 pa c07 d2a f07 gnd j07 gnd m07 br6 r07 br3 c08 fs2 f08 gnd j08 gnd m08 v ddext r08 rd c09 fs3 f09 gnd j09 gnd m09 wr r09 clkout c10 l0dat[6] f10 gnd j10 gnd m10 sda10 r10 hbr c11 l1dat[7] f11 v ddint j11 v ddext m11 ras r11 hbg c12 l1dat[3] f12 data[37] j12 data[26] m12 ack r12 clkdbl c13 l1dat[1] f13 data[40] j13 da ta[24] m13 data[17] r13 xtal c14 data[45] f14 data[ 38] j14 data[25] m14 dmag1 r14 sdwe c15 data[47] f15 data[ 36] j15 data[27] m15 dmag2 r15 nc 26 rstout exists only for silicon revisions 1.2 and greater. leave this pin unconnected for silicon revisions 0.3, 1.0, and 1.1.
adsst-sh arc-mel-100 rev. 0 | page 25 of 28 pin l a y o u t summar y v ddint v ddext gnd 1 agnd avdd signal 1 use the center block of ground pins to provide thermal pathways to the printed circuit board ground plane key: 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 r p n m l k j h g f e d c b a f i g u re 21. 22 5-l e a d m e t r i c m b g a pin a s s i g n ment s, bot t o m vi ew , su m m ar y
adsst-sh arc-mel-100 rev. 0 | page 26 of 28 outline dimensions 0.70 0.60 0.50 1.70 ma x 1.00 bsc a b c d e f g h j k l m n r p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 seating plane 1.10 ma x 0.20 max coplanarit y detaila ball diameter 0.30 min 17.00 bsc 17.00 bsc top view bottom view pin 1 indicato r pin 1 corne r 14.00 bsc sq notes: 1. dimensions are in millimeters. 2. actual position of the ball grid is within 0.25 of its ideal position relative to the package edges. 3. actual position of each ball is within 0.10 of its ideal position relative to the ball grid. compliant to jedec standards mo-192-aaf 2 detail a f i g u re 22. 22 5-ba l l m i ni-b a ll g r id a r r a y [m bg a ] (ca-22 5) di me nsio ns sho w n i n mi ll im e t e r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. ordering guide table 9. part number 27 , 28 case tempera t u re range instruction rate on-chip sram operating voltage adsst-me l -100 0c to +85c 100 mhz 0.5 mbit 1.8 v int/3.3 v e x t 27 these parts are pa ckaged in a 225- lea d mini-ball gr id arr a y (mbga). 28 th ese pro d uct s a r e so ld a s pa rt of a ch i p set , bun d le d wi t h n e cessa ry a ppli c a t i o n so ft wa re un der speci a l pa rt n u m b e r s. con t a ct a d i d i rectl y for more information.
adsst-sharc-mel-100 rev. 0 | page 27 of 28 notes
adsst-sh arc-mel-100 rev. 0 | page 28 of 28 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03681C0 C 10/03(0)

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